Layout Methodology Impact of Resolution Enhancement Techniques
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This paper introduces resolution enhancement techniques (RET), discusses the impact that RET have on the physical design and chip layout flow, and proposes two alternative future methodologies.
Resolution enhancement technologies
Resolution enhancement technology
Physical design (electronics)
15 Figures and Tables
Table 1, λ/NA solutions for recent technology nodes , illustrating the constant erosion of k1 for both technology development (Dev.) and manufacturing (Man.) *Potential Solution
Figure 1, Principle of attenuated phase shifted mask (attPSM)
Figure 2, Optical proximity correction
Figure 3, diagram of conventional, DRC-enabled layout flow
Figure 4, altPSM (left) and OAI (right) produce 2-beam imaging
Figure 5 Principle of altPSM
Figure 6 Double exposure altPSM
Figure 8 Sraf-enhanced layout showing local sraf conflicts
Figure 9 Simple layout forcing complex design rule
Figure 11. Example of cell level RET-embedded layout flow
Figure 13, Illustration of challenges for RET-aware routers.
Figure 14. Flow based on ‘radically restricted design rules’.
Figure 15. Optimization at design (right) and layout level (center)
Figure 16. Latch cell designed with RDR (left) is simultaneously altPSM optimized (cntr) and OAI-attPSM-SRAF optimized (right).
Figure 17. Gridded-layout placement.
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