Turbo-like codes not only achieve near Shannon-capacity performance, but also have decoders with modest complexity, which is crucial for implementation. Recently some efficient architectures for high-speed decoding of turbo and LDPC codes have been presented in the literature. The memory access is the main problem in practical implementation of such decoders. This problem has also been solved by using interleaves with special structure. In this paper, a generalized class of turbo-like codes that have high-speed decoding capability, which is based on the graphical interpretation of their code, is introduced. It has been shown that previous codes are part of this class. This class of codes not only provides code structure for parallel processing, but also provides the interleaver structure for practical implementation. A general architecture for high-speed decoding of these codes is presented. Regularity and modularity of the decoder makes it the architecture of choice for VLSI implementation of very high-speed decoders.
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